Meeting Update: Monday April 1, 2013

Updates:

Possibly Useful New Tool from Rice University: HPCToolkit (CGO'11, ISPASS'13, hpctoolkit.org, installed at rice, UMich, etc.)˘

  • Can break cache miss latency down to each variable.
  • Latency is read at register.
  • Every 64,000th instruction (randomly - on average), latency is read.

A single instruction records what happens to it (hit or miss).

With interest, I may be able to install this on one or more CRC or physics machines.

Should be able to continue working on RubyBEAR next week after midterm and paper resubmit deadline.

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